Today solved a very basic problem. In the forum, I saw someone asking the following code to report an error:
Define plus 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define unegate 3'd4
Module alu(opcode,out,a,b);
Input[2:0]opcode;
Input [7:0]a,b;
Output[7:0]out;
Reg[7:0]out;
Always@(opcode or a or b)
Begin
Case(opcode)
Plus:out=a+b;
Minus:out=ab;
Band:out=a&b;
Bor:out=a|b;
Unegate:out=~a;
Default:out=8'hx;
Endcase
End
Endmodule
Display error: Error (10161): Verilog HDL error at alu.v(14): object "plus" is not declared

First of all, plus 3'd0 should be 3'b0, otherwise it is followed by t[2:0]opcode; the number of digits cannot correspond to the syntax. There is no problem with the syntax, but the compilation does prompt the error to change `define to reg or parameter. In the end, I understand that the variable defined by `define unegate 4 must be `plus" when it is referenced. Haha, it turned out to be a small `symbol.

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