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The Distributed Wireless Communication System (DWCS) leverages distributed antennas, centralized processing control, and joint signal processing techniques to enhance both spectrum and power efficiency. This approach also boosts the system's flexibility and scalability, making it well-suited for modern communication demands.
The concept of network radio is central to the design of DWCS. Network radio refers to a general-purpose computing platform interconnected via optical fibers, forming a high-performance cluster capable of handling complex signal processing and control tasks. Similar to software-defined radios, this architecture offers a flexible structure, strong scalability, and faster computational capabilities, enabling higher network throughput.
In traditional software radio systems, general-purpose processors are often specialized devices such as DSPs or FPGAs. However, in the soft base station system presented in this paper, PC workstations are used as the primary signal processing units. Table 1 provides a detailed comparison of the advantages and disadvantages of using DSP/FPGA versus PC workstations in this context.
**Table 1: DSP vs. PC Workstation Performance Comparison**
The structure of this paper is organized as follows: First, the system architecture of the soft base station and its required hardware and software components are introduced. Then, key challenges in the design and implementation of the soft base station are discussed, including network throughput, sub-module processing rates, and overall system performance. Finally, practical solutions and system performance analysis are provided.
### 1. Soft Base Station System Design
#### 1.1 System Block Diagram
Figure 1 illustrates the overall system framework. The mobile station consists of a video terminal and a transmitter, while the base station includes six receivers and a cluster of PC workstations. A camera captures real-time video, which is then processed by the transmitter and sent through the wireless channel. Upon receiving the signal, the base station’s receivers forward the data to the workstation for processing, and finally, the output is displayed at the terminal. In practice, the system is transparent to the type of traffic, supporting not only video but also other forms of data transmission.
**Figure 1: System Architecture Diagram**
#### 1.2 Computing Cluster Configuration
The computing cluster comprises two identical PC workstations, each equipped with an AMD Sempron 2500+ processor (64-bit), 512MB DDR400 memory, and a 100Mbps network interface. The software platform runs on Red Hat 9.0 with kernel version 2.4.20-8. To improve signal processing speed, certain modules utilize Intel’s SSE and SSE2 instruction sets, requiring a compiler like GCC 3.3.1.
### 2. Key Problem Analysis and Performance Testing
#### 2.1 A/D Throughput Bottleneck
After analog-to-digital (A/D) conversion, the amount of data generated is extremely large. For example, an 8-bit, 50MHz A/D converter produces a data rate of 400 Mbps. With six receivers operating simultaneously, the total data rate could reach up to 2.4 Gbps, which is difficult to support over existing networks.
To address this, the system preprocesses the A/D data before sending it to the PC. Each receiver performs initial signal processing, converting RF signals into baseband signals to reduce the data rate. These receivers, based on FPGAs, handle functions such as digital down conversion, frame synchronization, and automatic gain control (AGC).
By preprocessing the signal, the data rate is reduced from 400 Mbps to 3.25 Mbps per receiver. For six receivers, the total rate becomes 19.5 Mbps, which is manageable within standard network conditions.
**Figure 2: Signal Processing Module Logic Diagram**
The receiver performs initial processing, including A/D sampling and downconversion, while more complex tasks are handled by the computing cluster.
#### 2.2 Submodule Throughput Optimization
The signal processing modules on the PC workstation include channel quality estimation, single-carrier frequency domain equalization, descrambling, deinterleaving, and TPC decoding. Due to the limited computing power of PCs, some submodules may operate too slowly, affecting overall system performance.
Table 2 shows the maximum throughput of each module under current system settings. During testing, only one module was run at a time to measure peak performance. It can be seen that Ethernet reception, channel quality estimation, and frequency domain equalization operate at around 12 MB/s, while TPC decoding is slower, reaching about 3.5 MB/s. When all modules are combined, TPC decoding will likely become the bottleneck.
**Table 2: Maximum Throughput of Each Submodule (MB/s)**
Although TPC decoding is slower than other modules, it still exceeds the chip rate of 1.625 MB/s. All modules meet the required throughput to satisfy the system design.
For submodules with low throughput, two approaches can be taken:
1. Improve the program efficiency, such as optimizing data stream processing using the Pentium instruction set (SSE/SSE2).
2. Split the module into smaller parts and distribute them across multiple PCs to increase processing speed.
#### 2.3 System Operating Rate
The system’s overall operating rate is generally lower than the highest individual submodule rate due to resource contention and data transfer overhead between modules. Table 3 presents the measured system throughput when all modules are running together. The system includes four main modules: channel quality estimation, single-carrier frequency domain equalization, and TPC decoding.
During testing, the modules were assigned to two PCs in different configurations. PC1 and PC2 refer to the two workstations used.
**Table 3: Workstation Throughput Test**
The optimal module allocation strategy involves running TPC decoding on a single PC, while the remaining modules are assigned to another. This configuration allows the system to achieve a throughput of 3.01 MB/s. Since TPC decoding is the most computationally intensive module, dedicating a PC to it ensures sufficient resources and improves system performance.
When scheduling modules, it's important to allocate more resources to complex tasks and place adjacent modules on the same PC to minimize network overhead.
### Summary and Outlook
This paper thoroughly examines the challenges in designing a DWCS soft base station, proposes practical solutions, and evaluates the system’s performance. The final results show that the system achieves a relatively high signal processing rate of 3.0 MB/s, meeting the design requirements.
The author introduces several innovations, including studying the characteristics of the new DWCS system and implementing PC workstations in the base station for the first time. The research and implementation of a complete DWCS communication system, along with real-world performance testing, have significant implications for the development of the DWCS system.
August 29, 2025